As the number of transistors per processor increases following the Moore’s Law, processor’s demand for power also increases. Along with this, the demand for better performance in processors has also grown. What’s more critical is that for energy efficiency and better performance and reliability, the operating voltage of processors has lowered down to between 1 – 2V. This poses major design challenges in the dc-dc converter, known as Voltage Regulator Module or VRM for short, that supplies power to these processors. Therefore, there is an urgent need for new topologies beyond the existing basic Multiphase Buck VRM topology that would effectively address these design challenges.

There are several new VRM topologies currently being developed in the Power Electronics Lab at Cal Poly. Prototypes of two of these new topologies have been successfully built and tested. Results from the two prototypes show promising performance which includes very low peak to peak output voltage ripple, and extremely tight load and line regulations, while maintaining fast dynamic response. Cal Poly, through the Graduate and Research Office, has applied for the US Patent for the two new topologies. The rest of the new topologies are currently being studied and developed.

For further information, or if interested, please contact Dr. Taufik.

For More Information

Dr. Taufik
taufik(place an 'at' sign here)calpoly.edu