Company:
Stanford University
Posted: June 06, 2008
Deadline: N/A
Description
SOC Verification
We are looking for a number of part-time or full-time verification engineers to help verify our Ultra-Wideband (UWB) SOC Design.
Requirements:
- MS in EE or CS
- Functional Verification Experience
- Knowledge of Verilog necessary
- Knowledge of PCI Express, SDIO and SystemVerilog desirable, but not necessary
Interested candidates please send email with resume to pathung@stanford.edu.
EXCITING SUMMER JOB
We are looking for a number of talented and motivated students to develop architectural models for the next-generation USB (USB 3.0) host controller and devices.
Requirements:
- MS/PhD students in EE or CS
- Knowledge of Verilog/C++ necessary
- Knowledge of SystemVerilog/SystemC desirable but not mandatory
Interested candidates please send email with resume to pathung@stanford.edu.